In a radio receiver, and in other systems where digital data is transmitted as analog pulses, it is common practice to convert the received analog data signal to a digital data output signal using a reference signal and a comparator that compares the analog signal with the reference signal. When the analog signal is greater than reference signal, the digital data signal is generated at a high voltage level, and when the analog signal is less than the reference signal, the digital data signal is generated at a low voltage level. In this way, the digital data encoded in the analog signal is decoded and presented in a usable form to a downstream digital circuit.
To account for different analog signal strengths, the reference signal in most receiver circuits is derived from the received analog signal using a circuit referred to as a slice level detector. That is, if a fixed reference signal were used to determine the digital data, then weaker and stronger analog signals would tend to produce different digital data. To avoid this problem, a slice level detector is used to generate a sliced level reference signal that adjusts to the signal strength of the received analog signal, thereby facilitating more reliable conversion of both weaker and stronger signals to corresponding digital data.
Two examples of receiver circuits utilizing conventional slice level detectors are described below with reference to FIGS. 6 and 7.
FIG. 6 is a simplified representation showing 40 including a mean slice level detector 41 and a comparator 42. Analog signal modulation information (analog signal) S, which is treated using one or more filters and amplifiers, (not shown), is applied to the non-inverting input terminal of comparator 42, and is also transmitted to mean slice level detector 41. Mean slice level detector 41 includes an RC filter that filters analog signal S to produce a mean slice level signal VSLICE-MEAN, which includes only the mean voltage level of analog signal S. Mean slice level signal VSLICE-MEAN is applied to the inverting input terminal of comparator 42 for use as a reference that adjusts with the level of analog signal S. That is, when analog signal S is strong, mean slice level signal VSLICE-MEAN is generated at a relatively high voltage level that represents the mean voltage level of the stronger analog signal, and when analog signal S is relatively weak, mean slice level signal VSLICE-MEAN is generated at a relatively low voltage level that represents the mean voltage level of the weaker analog signal. In this way, both weak and strong analog signals S are reliably consistently decoded and presented in a usable form to a downstream digital circuit (not shown).
In an alternative embodiment, peak slice level detectors may be employed to measure the positive and negative signal peaks of the received analog signal, and to generate an intermediate peak level signal (referred to herein as a “peak slice level reference signal”) that can be established more rapidly. FIG. 7 is a simplified representation showing a receiver circuit 50 including a conventional peak slice level detector 51 and a comparator 52. Analog signal S is applied to the non-inverting input terminal of comparator 52, and is also transmitted to mean slice level detector 51. Peak slice level detector 51 includes a positive peak generator circuit 53 that utilizes a first comparator C1 and an associated transistor T1 and RC filter to generate a positive peak signal, and a negative peak generator circuit 54 that utilizes a second comparator C2 and an associated transistor T2 and RC filter to generate a negative peak signal. It is usual to employ filtering of the derived reference level (e.g., using the RC filters of peak slice level detector 51) prior to use as the data slicing comparator reference signal. The positive and negative peak signals are combined to generate peak slice level reference signal VSLICE-PEAK that is applied to the inverting input terminal of comparator 52 for use as the reference, and is also applied to one terminal of a filter capacitor C.
FIGS. 8(A) and 8(B) are timing diagrams illustrating how the mean level and peak detecting slice reference generation circuits of the prior art, illustrated in FIGS. 6 and 7, will tend to discharge towards a zero volt signal level during gaps between data bursts, leading to difficulty recovering undistorted data at the beginning of the next signal burst, and the possibility of unwanted transient noise on the output data. FIG. 8(A) shows a received analog signal S being characterized by a first signal burst between time T0 and T1, a second signal burst starting at time T3, and a signal gap (i.e., a period that does not include digital data) between times T1 and T3. FIG. 8(B) shows digital output signal VOUT, which is generated by comparator 52 (see FIG. 7) in response to analog signal S. A problem associated with conventional peak and mean slice level reference generation is that, as indicated in FIG. 8(A), peak slice level reference signal VSLICE-PEAK cannot be maintained in the absence of the data pulses associated with BURST 1, and starts to decay, as indicated by the downward slanting dashed line portion starting at time T1. At time T2 peak slice level reference signal VSLICE-PEAK drops to approximately zero volts, resulting in undefined noise being generated by comparator 52 prior to the next data transition (BURST 2) during times T2 and T3 (see FIG. 8(B)), and slice level reference signal VSLICE-PEAK not being optimum at the start of the following data burst (BURST 2, starting at time T3) with the possibility of severely distorted recovered data bits.
What is needed is a circuit and method for performing improved data slicing operations when gaps are present in a data stream.